How to Handle Gate Drivers to Improve Performance and Reliability of GaN Devices
GaN HEMTs are a vehicle to demonstrate power converters that achieve higher end-to-end efficiency than today's silicon-based solutions, 80+ standards for servers and cloud data centers, or USB PD Far exceeds the most stringent standards, such as the EU Code of Conduct Tier 2 standards for compatible external adapters.
Traditional silicon-based switch technology has demonstrated near-ideal performance with fast, low-loss switching. GaN devices are even more ideal, but cannot be used as a drop-in replacement for silicon. To take full advantage of the potential benefits of this technology, along with careful board layout, external drive circuitry must be matched to the GaN device.
Comparing GaN and Silicon Switches
Higher efficiency is the most important potential benefit of enhancement-mode GaN when compared to silicon (Si) switches. Unlike its depletion-mode counterpart, enhancement-mode GaN is a normally-off device, requiring a positive gate drive voltage to turn the device on. The high efficiency of enhancement-mode GaN derives from the low device capacitance and the fact that GaN can conduct current in the reverse direction (quadrant 3) but has zero reverse recovery charge, which is This is a major advantage in “hard switching” applications.
The low gate-source and gate-drain capacitances result in low total gate charge, enabling fast gate switching and low power consumption of the gate driver. Also, the low output capacitance results in low turn-off losses.
However, other differences that can compromise practical GaN performance are the lack of drain-source/gate avalanche capability and the relatively low absolute maximum gate voltage, which is about +/-20V for Si MOSFETs. Whereas GaN is typically only +/-10V.
Furthermore, the turn-on threshold (VGTH) of GaN is about 1.5V, which is much lower than about 3.5V for Si MOSFETs. If the source and gate voltages can be reliably controlled by external drive and load circuits, switching frequencies can be increased into the hundreds of kHz to MHz range while maintaining high efficiency, resulting in smaller magnetics and capacitors for higher power density. (W/in3) can be achieved.
GaN Gate Drive Is Key to Performance
Keeping the gate drive voltage within the absolute maximum ratings is not the only requirement. For fastest switching, typical GaN devices require an optimal VG(ON) of approximately +5.2V to reach full enhancement without consuming excessive gate drive power. Must be driven to value. The driver power PD is given by:
PD = VSW・f・QGTOT
where VSW is the total gate voltage swing, f is the switching frequency, and QGTOT is the total gate charge. GaN gates are capacitive in nature, but power is dissipated in the effective series resistance of the gate and the driver. Therefore, it is important to keep voltage swings to a minimum, especially at very high frequencies. QGTOT is typically a few nC for GaN, about 1/10th of Si-MOSFET values of equivalent ratings, which is one of the reasons why GaN can switch so fast. GaN devices are charge controlled, and for nanosecond switching with nanocoulomb gate charges, the peak current is on the order of amperes, so the driver must deliver this current while maintaining a precise voltage. yeah.
Theoretically, a GaN device turns off reliably at VGS=0, but in reality even the best gate drivers do not apply 0V directly to the gate. I have. Any series inductance L present in the source common to the gate drive loop causes an opposite voltage VOPP to gate according to the equation VOPP=-L di/dt. A false turn-on can occur when the source di/dt is high (Figure 1).
Off-state dV/dt can cause current to flow in the device's "mirror" capacitance, producing the same effect, but this effect is negligible in GaN. There are solutions that provide a negative gate-off voltage of about -2V or -3V, but this complicates the gate drive circuit, so careful board layout, using devices with a "Kelvin connection", and low profile This can be avoided by minimizing the package inductance, such as the leadless PQFN type.
High-side gate drive challenges
GaN devices are not necessarily optimal for all topologies, and are capable of reverse conduction, such as most “single-ended” flyback and forward types. , and are not suitable where the extra cost over Si-MOSFETs outweighs any small efficiency benefit.
However, "half-bridges" such as totem-pole bridgeless PFCs, LLC converters, and active-clamp flybacks, whether hard-switching or soft-switching, are the preferred topologies for GaN's properties.
All of these topologies have a "high-side" switch whose source is the switching node, so the gate drive is offset from ground by a high-voltage, high-frequency waveform with nanosecond edges. This gate-drive signal comes from a system-ground-referenced controller, so the high-side driver must include a level shifter with an appropriate withstand-voltage rating, typically 450V or higher.
High-side drive also requires a means of generating a low-voltage power rail referenced to the switching node, usually with a network of bootstrap diodes and capacitors. The dV/dt of the switching waveform stresses the driver, which can exceed 100V/ns for GaN. This induces a displacement current that flows through the driver to ground, creating a voltage transient across the series resistance and connecting inductance that can perturb the sensitive differential gate drive voltage. Therefore, the driver must have strong dV/dt immunity.
To maximize efficiency and immunity to destructive "shoot-through", the high-side and low-third devices of the half-bridge are driven with minimal dead time and never overlapping. need to do it. Therefore, the high-side and low-side drivers must be properly controlled to match the propagation delay.
For the low side, the ground of the driver should be connected directly to the source of the switch to avoid introducing common inductance with the Kelvin connection. Since the driver also has a signal ground, connecting to this point is not optimal and this method can be problematic. For this reason, the low-side driver may also be equipped with some method of isolation or some common-mode voltage immunity to separate the power and signal grounds.
Safe Isolation Required for GaN Drivers
Although low voltage applications are on the rise, for offline applications that require high voltage ratings of 600V and above for both device and driver GaN devices in enhancement mode are currently receiving the most attention. If the driver's input signals are generated by a controller with human-accessible connections via the communication interface, this driver requires safe isolation in compliance with the relevant regulations. This can be achieved with a high speed signal galvanic isolator with a suitable isolation voltage. In many AC-DC converters, the controller circuit is often the "primary reference," but in these configurations the driver signal edge rate and high-side and low-side matching becomes an issue.
Application Example - Active-Clamp Flyback
This is an example of an active-clamp flyback topology (Figure 2) that uses a high-side switch to harvest energy from the leakage inductance of the converter's transformer. Recirculate back to power.
Compared to "snubber" or hard zener clamp methods, the circuit for low power applications from 45W to 150W has higher efficiency, better EMI and cleaner drain waveform. Typical applications include travel adapters for USB PD mobile phones and laptops, and embedded power supplies.
Figure 2 shows ON Semiconductor's dedicated GaN gate driver, NCP51820, along with an active-clamp flyback controller, NCP1568 (details omitted). The driver features a +5.2V swing gate driver optimized for enhancement-mode GaN, both high-side and low-side regulated.
The common-mode voltage range of -3.5V to +650V on the high side and -3.5 to +3.5V on the low side and dv/dt immunity of 200V/ns are also provided by advanced junction isolation technology. Now possible. A level shifter is provided for low-side drive, allowing easy Kelvin connections if the source of the low-side device has a current-sense resistor. Driver waveform rise and fall times of 1 ns, maximum propagation delay of 50 ns, and independent source and sink outputs for high and low sides allow gate drive edges to be adjusted to optimize balance between EMI and efficiency can. In this topology, the high-side and low-side drives do not overlap, but have different pulse widths, allowing power conversion and regulation with drain clamping or zero voltage switching controlled by the NCP1568 device.